1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming replacement gate structures for semiconductor devices, such as planar and 3D devices, and the resulting semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as FinFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D FinFET device, typically comprises doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. In a planar FET device, the gate structure is formed above a substantially planar upper surface of the substrate. In some cases, one or more epitaxial growth processes are performed to form epi semiconductor material in recesses formed in the source/drain regions of the planar FET device. In some cases, the epi material may be formed in the source/drain regions without forming any recesses in the substrate for a planar FET device. The gate structures for such planar FET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device “A” that is formed above a semiconductor substrate B that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap F. The gate structure D is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device A. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D is the channel region of the FinFET device A. In a conventional process flow, the portions of the fins C that are positioned outside of the spacers E, i.e., in the source/drain regions of the device A, may be increased in size or even merged together (a situation not shown in FIG. 1) by performing one or more epitaxial growth processes. The process of increasing the size of or merging the fins C in the source/drain regions of the device A is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source/drain regions. Even if an epi “merger” process is not performed, an epi growth process will typically be performed on the fins C to increase their physical size. In the FinFET device A, the gate structure D may enclose both sides and the upper surface of all or a portion of the fins C to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer (not shown), e.g., silicon nitride, is positioned at the top of the fins C and the FinFET device only has a dual-gate structure (sidewalls only). The gate structures D for such FinFET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins C, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. In a FinFET device, the “channel-width” is estimated to be about two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width (for a tri-gate device). Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
In a typical replacement gate process, the sacrificial gate structure or “dummy gate” structure is formed by depositing (or growing) a layer of silicon dioxide (the sacrificial gate insulation material) on the substrate and depositing a layer of polysilicon or amorphous silicon (the sacrificial gate electrode material) on the layer of silicon dioxide. A layer of gate cap material (e.g., silicon nitride) is then typically deposited above the layer of sacrificial gate electrode material. A patterned etch mask, e.g., photoresist, is then formed above the gate cap layer and the stack of materials are etched to define the sacrificial gate structure (the gate insulation layer and the gate electrode material layer) and the gate cap positioned thereabove. The sacrificial gate structure has a line-type configuration. Importantly, using such a processing sequence, the sacrificial gate structure tends to be outwardly tapered, i.e., it is wider at the bottom of the sacrificial gate structure (near the substrate) than it is at the top of the sacrificial gate structure. Sidewall spacers are then formed adjacent such an outwardly-tapered sacrificial gate structure. Ultimately, the sacrificial gate structure will be removed so as to define a replacement gate cavity between two spacers. Unfortunately, in such a process flow, the replacement gate cavity will also have this same outwardly-tapered configuration wherein the cavity is narrower at the top of the cavity than it is at the bottom of the replacement gate cavity. Such an outwardly-tapered replacement gate cavity makes it extremely difficult to fill the cavity with the various layers of material that are deposited in the replacement gate cavity to ultimately form the replacement gate structure. For example, problems such as “pinch off” may occur in the gate cavity wherein the materials effectively block off portions of the cavity such that the blocked portions cannot be filled with the desired materials. This problem is anticipated to become more of an issue as device shrinking continues, thereby requiring smaller and smaller gate cavities that need to be filled.
Another problem as it relates to the formation of FinFETs is directed to the problem of adequately controlling the channel region of the device. In general, it would be desirable for the fin height in the channel region to be as tall as possible so that better control of the channel region may be obtained. However, since prior processes uniformly establish the fin height by recessing an insulating material, the resulting height of the fins is substantially uniform in the source/drain regions and in the channel regions. Additional fin height can be achieved by uniformly etching the layer of insulating material after the fins are formed, but such an etching process will further damage the fins and the interlayer dielectric material so etched.
The present disclosure is directed to various methods of forming replacement gate structures for semiconductor devices, such as planar and 3D devices, that may avoid, or at least reduce, the effects of one or more of the problems identified above.